The present invention relates to a performance control apparatus and more particularly to a performance control apparatus that can modify performance in accordance with the rate of operation of an instruction processor.
In the construction of a computer system, the processing power or the maximum processing speed of a computer is determined to match an expected maximum amount of operation. On the other hand, in operation, the rate of operation is monitored to examine the sufficiency of the processing power and the data monitored and the like are collected to be stored as operation history. The stored data can be analyzed to thereby extremely eliminate impediment to operation due to lack of the processing power.